Issue link: https://industrialengineer.epubxp.com/i/920036
January 2018 | ISE Magazine 53 when a model is fit too much to the noise part in the historical data, so that even if the model has a smaller training error, it loses its power for prediction, leading to a greater error when used on new observations. Adding physical con- straints appears to be an effective way to avoid reading too much to noise (and thus avoid overfitting). In the era of big data, the most effec- tive way to tackle engineering challeng- es is to combine engineering knowledge with sophisticated data science methods. Imposing shape or sign constraints in a data science model, including non- negativity/non-positivity, monotonicity and convexity/concavity, among others, is a systematic way to accomplish that goal. CONTACT: Yu Ding; yuding@tamu.edu; (979) 458-2343; ETB 4016, MS 3131, Department of Industrial and Systems Engineering, Texas A&M; University, College Station, TX 77843-3131 Can different defect patterns be recognized when they are mixed over a wafer? The wafer fabrication process consists of multiple sequential processes, such as oxidation, photolithography, etching, ion implantation and metallization. Af- ter wafer fabrication, a verification test is performed on each die of a wafer to detect any process change and to verify whether all dies meet product specifica- tions. Based on wafer test results, each die can be assigned a binary value (e.g., value one for good dies and value zero for defective dies). The resulting spatial map of a wafer is called a wafer bin map (WBM). The bin values of adjacent dies in a WBM are often spatially correlated, forming some systematic defect patterns (e.g., circle, ring, scratch, shot and zone pat- terns). These nonrandom defect pat- terns occur because of assignable causes. For example, a circular pattern concen- trated in the center of a wafer typically occurs when a chemical mechanical process causes uniformity variations. Therefore, it is important to identify systematic defect patterns in order to know the root causes of failure and to take actions for quality management. In particular, as wafer-fabrication processes have become more com- plicated, mixed-type defect patterns (two or more different types of defect patterns occurring simultaneously in a single wafer) occur more frequently than in the past. For more effective classification of wafers according to their defect patterns, mixed-type de- fect patterns need to be detected and separated into several clusters of differ- ent patterns. Subsequently, each cluster of a single pattern can be matched to a well-known defect type (e.g., circle, ring), or it may indicate the emergence of a new defect pattern. However, there are several challenges: The separation of random defects from systematic de- fect patterns, determining the number of clusters and the clustering of defect patterns of complex shapes. This problem is investigated in the paper "Detection and clustering of mixed-type defect patterns in wafer bin maps," by Jinho Kim, a project leader of DRAM test engineering team at SK hynix, Youngmin Lee, a Ph.D. student at KAIST, and Heeyoung Kim, an assistant professor at KAIST. To de- tect systematic defects before they are clustered, the authors propose a new fil- tering method. Called connected-path filtering, the method aims to detect paths that are longer than a prespeci- fied threshold. Then random defects can be removed. The detected system- atic defects are subsequently clustered using the infinite warped mixture model. This model can effectively clus- ter mixed-type defect patterns with complex shapes, and furthermore the number of clusters does not need to be specified in advance but is automati- cally determined during the clustering procedure. The proposed method was tested on real WBM data from SK hynix, a global semiconductor company, and the results demonstrate that the pro- posed method can successfully separate mixed-type defect patterns into several clusters of different patterns with the right number of clusters. CONTACT: Heeyoung Kim; heeyoungkim@kaist. ac.kr; 82-42-350-3125; Department of Industrial and Systems Engineering, KAIST, 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea Youngmin Lee (from left), a Ph.D. student at KAIST, Heeyoung Kim, an assistant professor at KAIST, and Jinho Kim, a project leader of a DRAM test engineering team at SK hynix, collaborated for a better way to find mixed-type defects in semiconductor wafers.